Variable gain amplifiers are well known in the art. Typically, they are designed for digital gain control and for use in telecommunication circuits such as GSM (Global System for Mobile Communication) telephone receivers. Such circuits operate at high frequencies such as 246 MHz.
One common prior art circuit for providing a digitally controlled gain is shown in FIG. 1. A plurality of transconducting amplifiers 12(a-h) are connected to a pair of common output resistors RL. The output currents are switched either into or away from these output resistors to control the gain. As shown, for example, in FIG. 1, a variable gain amplifier (VGA) 10 of the prior art comprises a plurality of eight (8) transconductance amplifiers 12(a-h) connected in parallel. Each of the transconductance amplifiers 12(a-h) receives the input signals +IN and -IN. Each of the transconductance amplifiers 12(a-h) generates a pair of output signals which are supplied to an associated switch 14(b-h). Since the VGA 10 has to have at least one stage of amplification, the output of the first stage amplifier 12a has its associated switch 14a in the closed position at all time. The outputs of each of the associated switches 14(b-h) are then connected in parallel to a pair of output buses -OUT and +OUT, which are connected to a pair of resistors RL.
Each of the eight amplifiers 12(a-h) provides an output current which is proportional to the voltage input. Except for the first amplifier 12a, each of the other amplifiers 12(b-h) may be selectively connected to the load resistors RL to augment the gain of the other amplifiers. Each of the amplifiers 12(b-h) provides an additional two dB gain when its associated switch 14(b-h) is closed. Set forth below is a chart showing the switch settings necessary to program the gain from -3 dB to +11 dB in 2 dB steps (assuming that each of the amplifiers 12 can amplify in 2 dB gain increment).
TABLE I __________________________________________________________________________ Gain vs. Switch Setting GAIN SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 __________________________________________________________________________ -3 dB CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED -1 dB OPEN CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED +1 dB OPEN OPEN CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED +3 dB OPEN OPEN OPEN CLOSED CLOSED CLOSED CLOSED CLOSED +5 dB OPEN OPEN OPEN OPEN CLOSED CLOSED CLOSED CLOSED +7 dB OPEN OPEN OPEN OPEN OPEN CLOSED CLOSED CLOSED +9 dB OPEN OPEN OPEN OPEN OPEN OPEN CLOSED CLOSED +11 dB OPEN OPEN OPEN OPEN OPEN OPEN OPEN CLOSED __________________________________________________________________________
As the switch 14(b-h) associated with each amplifier 12(b-h) is closed, it contributes a current into the output resistors RL which increases the output signal by 2dB.
Referring to FIG. 2, there is shown a detailed schematic circuit diagram of the VGA 10 of the prior art whose block diagram is shown in FIG. 1. The transistors 20a and 20b are commonly used in a cascode configuration connecting the collector of the transistors 18 of the amplifiers 12(a-h) to the output lines +OUT and -OUT. This is to improve the bandwidth. The associated switches 14(a-h) are typically implemented as transistors. As previously discussed, the base for the transistors shown in switches 14a1 and 14a2 would be connected to ground which is in the "ON" position thereby "permanently" connecting amplifier 12a to receive the input signals +IN and -IN and to generate output signals supplied to the output lines +OUT and -OUT. The emitters of the switches 14 are connected to the emitters of the associated amplifier 12 and the collectors are connected to the collectors of the associated amplifier 12. The purpose of the transistors in the switches 14(a-h) is to shunt the current from the current sources 16 around the transistors 18 and directly to the buses 22a and 22b, thereby giving a zero transconductance for the amplifying stage.
The collectors of the switches 14(a-h) are connected to the collectors of the transistors 18 of the associated amplifier 12 rather than to a power supply to keep the DC current level in the load resistors RLA and RLB substantially constant so that the DC output voltage does not vary substantially as a result of selecting a new gain. Finally, of course, the switches 14(a-h) associated with each amplifier 12(a-h) can be switched to turn on or off the associated current sources 16.times.1 and 16.times.2 associated with each amplifier, instead of using switching transistors as shown in FIG. 2.
The prior art VGA circuit 10 works relatively well for high gains. However, when all the switches are off (except for switch 14a) which results in low gain, the collector-base capacitance of the "OFF" amplifying transistors 18 in each of the amplifiers 12(b-h) would still be present. Thus, the collector-base capacitance of transistors 18(b-h)2 and 18(b-h)1 for the amplifiers 12(b-h) would still be present even though the associated switches 14(b-h) are off. This collector-base capacitance provides a feedforward path for the signal from the inputs +IN and -IN directly to the common collector buses of 22a and 22b. If minimum gain is desired, i.e. only one amplifier stage (amplifier 12a) is on then the other seven amplifiers 12(b-h) would contribute substantial unwanted signal current through this collector-base capacitance. As a result, this feedforward current produces an unwanted peaking in the frequency response of the VGA amplifier 10 as shown in FIG. 3. As frequencies increase, more and more current flows through the collector-base capacitors resulting in a peak in the frequency near the bandwidth limit of the amplifier. This problem is more severe at the lowest gain where most of the amplifiers are supposed to be off but instead pass this unwanted feedforward current. The problem is least severe at high gains where the VGA amplifier 10 is supposed to pass the signal anyway.
Referring to FIG. 4, there is shown an analog multiplexer 30 of the prior art. This is shown and is described in U.S. Pat. No. 5,352,987. The analog multiplexer 30, instead of having a common pair of input buses, receives a plurality of pairs of input signals such as IN.sub.A1, IN.sub.A2 ; IN.sub.B1, IN.sub.B2 . . . IN.sub.N1, and IN.sub.N2. Each pair of input signals is supplied to the base of a pair of first transistors, whose emitters are connected to a current source. The collectors of the pair of first transistors are connected to the emitters of a pair of control transistors whose bases are supplied with a control logic signal. The collectors of the control transistors are tied to a fixed voltage. The common nodes of the collectors of the first transistors and the emitters of the control transistors are then connected to the emitters of a pair of second transistors whose bases are tied to a bias voltage. Finally, the collectors of the second transistors are connected to the output of an amplifier. In this manner, the base-emitter capacitance of the second transistors effectively couples the high frequency signal to the bias supply connected to the bases of the second transistors and is effectively shunted away from the inputs to the main amplifier (see Col. 2, lines 65-Col. 3, line 2).